Traffic controller employing a digital computer

ABSTRACT

A traffic controller employing several circuit means for providing information to and from a digital compupter for controlling signalization at an intersection including two or more movements of traffic. A first of the circuit means includes circuits for inputting manual commands to the computer and for displaying the existence of such commands and others on a board associated with each of the movements of traffic. A second circuit means is provided for creating a timing function for use in controlling the signalization, and third circuit means is provided for displaying and changing the time duration of several functions in each of the separate movements of traffic.

United States Patent Spilo et al.

I TRAFFIC CONTROLLER EMPLOYING A DIGITAL COMPUTER Inventors: Richard A. Spilo, Davenport, Iowa;

Frank W. Hill, Moline; Larry O. Hoffman, Rockford, both of Ill.

[73] Assignee: Gulf & Western Industries, Inc.,

New York, NY.

[22] Filed: Feb. 20, 1974 [2]] Appl No.: 444,122

Related US. Application Data 1 May 27, 1975 Primary Examiner-Thomas B. Habecker Attorney, Agent, or Firm-Meyer, Tilberry & Body [57] ABSTRACT A traffic controller employing several circuit means for providing information to and from a digital compupter for controlling signalization at an intersection including two or more movements of traffic. A first of the circuit means includes circuits for inputting manual commands to the computer and for displaying the existence of such commands and others on a board associated with each of the movements of traffic. A second circuit means is provided for creating a timing function for use in controlling the signalization, and third circuit means is provided for displaying and changing the time duration of several functions in each of the separate movements of traffic.

45 Claims, 45 Drawing Figures PATENTEUMAYZT I915 3,886,496

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sTART 300 032E JPC INIT INITIALIZE SYSTEM REsET "INITIAuzE sYsTEM" FF 302 588E xI sER XYZ 304 5RD Exc 0,29

UPDATE PANEL 30s E880 JMC .PAN

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30E 4502 sss am 0300 JPC x3 wAIT FOR I/IO sEcOND 3I2 5I37 Exc I,23 ACKNOWLEDGE CLOCK UPDATE INPUTs FROM SCAN DETECTOR 3I4 E380 JMC .scD 3l6 EDOC JMC .OMs JUMP To OMIT SKIP OPTION UPDATE PI-IAsE TIMINGS 318 E4D0 JMC .PUP

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ADvANcE FROM RED 324 650 JMC .AFR

UPDATE DISPLAY 326 760 x2 JMC .DUP

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SHEET FIG. 26

FIG. 2F

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1. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a memory unit to store at separate addresses, separate binary codes each representing a numerical value for use in a selected function of said controller, the improvement comprising: a switching network for manually selecting, from one of said addresses, one of said codes for a selected function; means for decoding said selected code to produce display numerals corresponding to the numerical value at said one address; a visual display means for displaying said display numerals; means for manually changing said display numerals displayed by said visual display means to a new value; means for providing a new code corresponding to said new value; and, means for then storing said new code in said memory unit at said one address.
 2. The improvement as defined in claim 1 wherein said switching network includes a plurality of switches with the closure of a selected one or more of said switches corresponding to a selected function; means for allowing actuation of said switches corresponding to a single function at any given time; a encoding circuit for encoding said network to provide an output representative of the function selected by actuation of a switch or switches in said network; and means responsive to said output for addressing said memory unit to said one address.
 3. The improvement as defined in claim 1 wherein said manual changing means includes a binary counter means having an input means for receiving said selected code from said memory unit and representative of the numerical value stored in said memory unit for said selected value and an output means connected to said decoding means for directing said selected code as output binary coded information to said decoding means, manually actuated counting means for changing successively by a single digit said output binary coded information to produce said new code and said memory storing means including Means for selectively substituting said new code into said memory unit at said one address.
 4. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a memory unit for storing separate binary coded representations of numerical values for use in a selected function of said controller at separate coded addresses in said memory unit, the improvement comprising: a switch circuit for creating an address corresponding to one of said selected functions, circuit means for directing a coded signal corresponding to said address to said memory unit to create said binary representation of said one selected function in a series of parallel output lines; a decoder means for decoding said output lines and having an output means for creating a 7-Bar decoded representation of said binary representation in said parallel lines; and a 7-Bar display device for receiving said 7-Bar decoded representation and displaying digits corresponding with said decoded representation.
 5. The improvement as defined in claim 4 including means for receiving said binary representation of said one selected function and means for manually converting said binary representation of said one selected function into a new binary representation and means for storing said new representation at said address of said memory unit.
 6. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a memory unit for storing binary coded representations of a numerical value for use in a selected function of said controller at separate coded addresses in said memory unit, the improvement comprising: a switch circuit for creating an address corresponding to one of said selected functions; circuit means for directing a coded signal corresponding to said address to said memory unit to create said binary representation of said one selected function in a series of parallel output lines; a counter means having an input connected to said parallel lines, a second series of parallel output lines, means for setting said counter means to a binary code in said second series of output lines corresponding to said binary representation in said first mentioned lines, means for manually changing the binary code in said second output lines; a decoder means for decoding said binary code in said second output lines and having an output means for creating a decoded representation of said binary code in said second output means; a display device for displaying a digit corresponding to said decoded representation; and, means for storing said binary code in said second output lines in said memory unit at said address of said selected function.
 7. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a memory unit for storing binary coded representations of a numerical value for use in a selected function of said controller at separate coded addresses in said memory unit, the improvement comprising: a switch circuit for creating an address corresponding to one of said selected functions; circuit means for directing a coded signal corresponding to said address to said memory unit to create said binary representation of said one selected function in a series of parallel output lines; updating means connected to said output lines for selectively changing at a pulsed rate said binary representation to a new binary code; and means for storing said new binary code in said memory unit at said address of said selected function.
 8. The improvement as defined in claim 7 wherein said updating means includes a binary counter having an output, a setting means connected to said output lines for setting said output to said binary representation of said one selected function, and means for successively clocking said counter to create said neW binary code in said output.
 9. In a controller for timing a selected duration of a particular function for a traffic signal displayed to one of at least two conflicting movements of traffic through an intersection, said duration comprising a known number of increments, said controller including a digital computer controlled by a preestablished program having a series of sequential steps comprising a program cycle, the improvement comprising: a timing system including a flip-flop having a first selected output upon being clocked and a second output; means for clocking said flip-flop periodically at a given rate having a known period corresponding to said increments; means for preventing progress of said program through said cycle when said flip-flop has said second output; means for allowing said program to progress through said cycle when said flip-flop has said first selected output; means for creating said second output when said program is allowed to progress; and means responsive to a number of said program cycles corresponding to said known number for timing said selected duration.
 10. In a controller for controlling a traffic signal displayed to one of at least two conflicting movements of traffic through an intersection, said controller including a digital computer controlled by a preestablished program having a series of sequential steps comprising a program cycle, the improvement comprising: a circuit external of said computer for controlling the time of the program cycle to a preselected, known time; said circuit including means for creating a control signal at a known rate corresponding to said known time; means for sensing the existence of said control signal; a program initiated sensing means for controlling said cycle time in response to the sensed existence of said control signal; and, said external circuit comprising a flip-flop having an output; means for clocking said flip-flop to produce said control signal at said output; means for actuating said clocking means at said known rate; and, means responsive to said output of said flip-flop for clearing said flip-flop whereby said control signal is removed from said output.
 11. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a digital computer with a memory unit, a lead connected to said computer, means for inputing traffic information into said computer on said lead and means for outputing signalization information from said computer on said lead, the improvement comprising: said outputing means including an output line means connected to said lead for outputing a single bit of binary information from said computer; and said inputing means including a first logic gate having a first input line means for inputing a single bit of input information to said logic gate; a second input line means for enabling said logic gate; and an output lead means for outputing a bit of binary information corresponding to said input information on said first input line means when said logic gate is enabled by said second input line means; and, a switch means connected to said output line means for controlling the logic state of said lead in accordance with the condition of said switch means, said switch means having a condition controlling means connected to said output lead of said logic gate and means for controlling the condition of said switch means in response to the single bit of binary inforamtion on said output lead means of said logic gate.
 12. The improvement as defined in claim 11 including a second logic gate having first and second input leads and an output lead, means for connecting said output lead of said second logic gate with the first input line means of said first logic gate, means for enabling said first input lead of said second logic gate, and means for applying a logic signal corresponding to said traffic information to said second input lead of said second logic gate.
 13. The iMprovement as defined in claim 12 wherein said means for applying a logic signal to said second input lead includes an interface circuit comprising an input portion for receiving a logic state corresponding to said traffic information, an output portion connected to said second input lead of said second logic gate, and means for interconnecting said input portion and said output portions, said interconnecting means including a radiation source, means for actuating said source in response to traffic information applied to said first portion and a radiation responsive means exposed to said radiation source for actuating said output portion in response to actuation of said radiation source.
 14. The improvement as defined in claim 13 wherein said interconnecting means includes a voltage breakdown circuit having an input connected to said first portion, a grounded output and a voltage breakdown device in series with said input and said output of said breakdown circuit.
 15. The improvement as defined in claim 11 including an interface circuit comprising an input portion for receiving said single bit of input information, an output portion connected to said first input of said first logic gate, and means for interconnecting said input and said output portions, said interconnecting means including a radiation source, means for actuating said source in response to traffic information applied to said first portion and a radiation responsive means exposed to said radiation source for actuating said output portion in response to actuation of said radiation source.
 16. The improvement as defined in claim 15 wherein said interconnecting means includes a voltage breakdown circuit having an input connected to said first portion, a grounded output and a voltage breakdown device in series with said input and said output of said breakdown circuit.
 17. The improvement as defined in claim 11 including a first D-type flip-flop having its D terminal connected to said output line means, a Q terminal and a clocking terminal; a second D-type flip-flop having its D terminal connected to the Q terminal of said first D-type flip-flop, a Q terminal connected to an output circuit having an output means for controlling one of said signals, and a clocking terminal; means for applying a first clocking pulse to said clocking terminal of said first flip-flop; means for applying a second clocking pulse to said clocking terminal of said second flip-flop; and means for creating said first clocking pulse prior to said second clocking pulse.
 18. The improvement as defined in claim 17 including means for creating said first clocking pulse with a first pulse rate and means for creating said second clocking pulse with a second pulse rate substantially more than said first pulse rate.
 19. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic throough an intersection, said controller including a digital computer with a memory unit to store separate binary logic for information corresponding to selected operations of the controller, the improvement comprising: an input-output circuit including an indicator light means for indication of a particular one of said selected conditions; means for actuating said indicator light means upon receipt of a first coded signal from said memory unit and corresponding to said one selected operation; first control means for activating said actuating means; a switch means for creating a second coded signal corresponding to a second of said selected operations; means for directing said second coded signal to said memory unit; second control means for activating said directing means; and, means for alternately actuating said first and second control means.
 20. The improvement as defined in claim 19 wherein said first control means is a D-type flip-flop having its D terminal connected to a lead means connected to said memory unit, a Q terminal forming said indicator light actuating means and a clocking terminal, and said first control means including means for applying a clocking pulse to said clocking terminal whereby the coded signal from said memory unit and at said D terminal is transmitted to said Q terminal.
 21. The improvement as defined in claim 20 wherein said directing means includes a logic gate having first and second inputs and an output, means for connecting said first input to said switch means for receiving a coded signal created by the position of said switch means; means for connecting said second input to said second control means, said second control means including means for selectively latching and unlatching said second input, and means connecting said output to said memory unit.
 22. The improvement as defined in claim 21 including pulsing means for alternately creating a first pulse and a second pulse, first pulse responsive means for actuating said first control means upon existence of said first pulse and second pulse responsive means for actuating said second control means upon existence of said second pulse.
 23. The improvement as defined in claim 22 wherein said pulsing means includes means for creating said first and second pulses at least one each approximately 0.1 seconds.
 24. The improvement as defined in claim 19 wherein said directing means includes a logic gate having first and second inputs and an output, means for connecting said first input to said switch means for receiving a coded signal created by the position of said switch means; means for connecting said second input to said second control means, said second control means including means for selectively latching and unlatching said second input, and means connecting said output to said memory unit.
 25. The improvement as defined in claim 24 including pulsing means for alternately creating a first pulse and a second pulse, first pulse responsive means for actuating said first control means upon existence of said first pulse and second pulse responsive means for actuating said second control means upon existence of said second pulse.
 26. The improvement as defined in claim 25 wherein said pulsing means includes means for creating said first and second pulses at least one each approximately 0.1 seconds.
 27. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a digital computer with a memory unit to store separate binary logic for information corresponding to selected operations of the controller, the improvement comprising: an output circuit including an indicator light means for indication of a particulalr one of said selected operations; means for actuating said indicator light means upon receipt of a coded signal from said memory unit and corresponding to said one selected operation; and control means for activating said actuating means, said control means being a D-type flip-flop having its D terminal connected to a lead means communicated with said memory unit, a Q terminal forming said indicator light actuating means and a clocking terminal, and said control means including means for applying a clocking pulse to said clocking terminal whereby the coded signal from said memory unit and at said D terminal is transmitted to said Q terminal.
 28. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a digital computer with a memory unit to store separate binary logic for information corresponding to selected operations of the controller, the improvement comprising: an input circuit including a switch means for creating a logic corresponding to one of said selected operations; means for directing said logic to said memory; and control means for activating said directing means, said directing means including a logic gate having first and second inputs and an output; means for connecting said first input to said switch means for receiving a coded signal created by the position of said switch means; means for connecting said second input to said control means; said control means including means for selectively disabling and enabling said second input, and means connecting said output to said memory unit.
 29. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a memory unit to store at separate addresses, separate binary codes each representing a numerical value for use in a selected function of said controller, the improvment comprising: a switching network for manually selecting from one of said addresses one of said codes for a selected separate numerical value; means for decoding said selected code to produce display numerals; a visual display means for displaying said display numerals; means for manually changing said display numerals displayed by said visual display means to a new value; means for providing a new code corresponding to said new value; and, means for then storing said new code in said memory unit at said one address.
 30. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a memory unit for storing binary coded representations of separate numerical values for use in a selected function of said controller at separate coded addresses in said memory unit, the improvement comprising: a switching circuit for creating a memory address corresponding to one of said functions; means for displaying a numerical value; means for creating a binary code corresponding to said displayed numerical value of said displaying means; means for changing said displayed value to a selected second displayed value; and, manually actuated switch means for storing said binary code at said created memory address.
 31. The improvement as defined in claim 30 including an element movable between first and a second position, and means responsive to said element being in said first position for inhibiting said storing means.
 32. The improvement as defined in claim 30 including a key operated element movable by a key between a first and a second position, and means responsive to said element being in said first position for inhibiting said storing means.
 33. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a memory unit for storing binary coded representations of a numerical value for use in a selected function of said controller at separate coded addresses in said memory unit, the improvement comprising: a switch circuit for creating an address corresponding to one of said selected functions; circuit means for directing a coded signal corresponding to said address to said memory unit to create said binary representation of said one selected function in a series of parallel output lines; a logic storing means having an input connected to said parallel lines, a second series of parallel output lines, means for setting said storing means to a binary code in said second series of output lines corresponding to said binary representation in said first mentioned lines, means for manually changing the binary code in said second output lines; a decoder means for decoding said binary code in said second output lines and having an output means for creating a decoded representation of said binary code in said second output means; a display device for displaying a digit corresponding to said decoded representation.
 34. The improvement as defined in claim 33 including means for storing said binary code in said second output lines in said memory unit at said address of said one selected function.
 35. In a controller for timing a selected duration of a particular function for a traffic signal displayed to one of at least two conflicting movements of traffic through an intersection, said duRation comprising a known number of increments, said controller including a digital means controlled by a preestablished program having a series of sequential steps comprising a program cycle, the improvement comprising: a timing system including a flip-flop having a first selected output upon being clocked and a second output; means for clocking said flip-flop periodically at a given rate having a known period corresponding to said increments; means for preventing progress of said program through said cycle when said flip-flop has said second output; means for allowing said program to progress through said cycle when said flip-flop has said first selected output; means for creating said second output when said program is allowed to progress; and means responsive to a number of said program cycles corresponding to said known number for timing said selected duration.
 36. In a controller for controlling a traffic signal displayed to one of at least two conflicting movements of traffic through an intersection, said controller including a digital means controlled by a preestablished program having a series of sequential steps comprising a program cycle, the improvement comprising: a circuit external of said digital means for controlling the time of the program cycle to a preselected, known time; said circuit including means for creating a control signal at a known rate corresponding to said known time; means for sensing the existence of said control signal; a program initiated sensing means for controlling said cycle time in response to the sensed existence of said control signal; and, said external circuit comprising a flip-flop having an output; means for clocking said flip-flop to produce said control signal at said output; means for actuating said clocking means at said known rate; and, means responsive to said output of said flip-flop for clearing said flip-flop whereby said control signal is removed from said output.
 37. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a digital means with a memory unit, a lead connected to said digital means, means for inputing traffic information into said digital means on said lead and means for outputing signalization information from said digital means on said lead, the improvement comprising: said outputing means including an output line means connected to said lead for outputing a single bit of binary information from said digital means; and said inputing means including a first logic gate having a first input line means for inputing a single bit of input information to said logic gate; a second input line means for enabling said logic gate; and an output lead means for outputing a bit of binary information corresponding to said input formation on said first input line means when said logic gate is enabled by said second input line means; and, a switch means connected to said output line means for controlling the logic state of said lead in accordance with the condition of said switch means, said switch means having a condition controlling means connected to said output lead of said logic gate and means for controlling the condition of said switch means in response to the single bit of binary information on said output lead means of said logic gate.
 38. The improvement as defined in claim 37 including a second logic gate having first and second input leads and an output lead, means for connecting said output lead of said second logic gate with the first input line means of said first logic gate, means for enabling said first input lead of said second logic gate, and means for applying a logic signal corresponding to said traffic information to said second input lead of said second logic gate.
 39. The improvement as defined in claim 37 including a first D-type flip-flop having its D terminal connected to said output line means, a Q terminal and a clocking terminal; a second D-type flip-flop having its D terminal connected to the Q terminal of said first D-type flip-flop, a Q terminal connected to an output circuit having an output means for controlling one of said signals, and a clocking terminal; means for applying a first clocking pulse to said clocking terminal of said first flip-flop; means for applying a second clocking pulse to said clocking terminal of said second flip-flop; and means for creating said first clocking pulse prior to said second clocking pulse.
 40. The improvement as defined in claim 39 including means for creating said first clocking pulse with a first pulse rate and means for creating said second clocking pulse with a second pulse rate substantially more than said first pulse rate.
 41. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a digital means with a memory unit to store separate binary logic for information corresponding to selected operations of the controller, the improvement comprising: an output circuit including an indicator light means for indication of a particular one of said selected operations; means for actuating said indicator light means upon receipt of a coded signal from said memory unit and corresponding to said one selected operation; and control means for activating said actuating means, said control means being a D-type flip-flop having its D terminal connected to a lead means communicated with said memory unit, a Q terminal forming said indicator light actuating means and a clocking terminal, and said control means including means for applying a clocking pulse to said clocking terminal whereby the coded signal from said memory unit and at said D terminal is transmitted to said Q terminal.
 42. In a controller for controlling traffic signals displayed to at least two conflicting movements of traffic through an intersection, said controller including a digital means with a memory unit to store separate binary logic for information corresponding to selected operations of the controller, the improvement comprising: an input circuit including a switch means for creating a logic corresponding to one of said selected operations; means for directing said logic to said memory; and control means for activating said directing means, said directing means including a logic gate having first and second inputs and an output; means for connecting said first input to said switch means for receiving a coded signal created by the position of said switch means; means for connecting said second input to said control means; said control means including means for selectively disabling and enabling said second input, and means connecting said output to said memory unit.
 43. A traffic signal controller for controlling a traffic signal for allocating right of way to a traffic movement passing through a controlled area wherein said right of way includes timed intervals for timing said right of way to a traffic movement, said traffic signal controller including: a memory unit having separate coded addresses to designate separate locations in said memory unit, each of said locations corresponding to one of said timed intervals; said memory unit including means for storing separate coded representations in said memory unit locations corresponding to the time duration that a selected one of said timed intervals is to be operative in said controller; manually actuatable switch means for selecting the memory unit coded address corresponding to a particular one of said timed intervals; means responsive to said switch means selected coded address for selecting the one of said stored separate coded representation in said memory unit at said location corresponding to said particular one of said timed intervals; means for decoding said selected separate coded representation into numerical display information represented by said selected separate coded representation; means for decoding said selected separate coded representation tO produce a timing value; and means for timing said particular one of said timed intervals in response to said decoded timing value.
 44. A traffic signal controller as defined in claim 43 including means for visually displaying said numerical display information representative by said selected separate coded representation as a number in a visual display device.
 45. A traffic signal controller as defined in claim 44 including means for changing said number in said visual display device; means for decoding said number into a new coded representation; and means for storing said new coded representation into the memory location corresponding to said switch selected memory unit coded address. 